1. Field of the Invention
The present invention generally relates to integrated circuits. More particularly, the present invention provides a fast/slow state machine latch that generates fast and slow select signals for a single toggle, low power multiplexer circuit.
2. Related Art
Many conventional multiplexers suffer from excessive power consumption due to invalid data signal transitions (e.g., glitches). To this extent, a low power multiplexer circuit has been developed that undergoes data signal transitions only for valid data signals, thus reducing power consumption. Such a low power multiplexer circuit is disclosed in U.S. Pat. No. 6,054,877, which is incorporated in its entirety herein by reference. Unfortunately, extensive education is required to understand the operation/implementation of this type of low power multiplexer circuit, thereby hindering its use and acceptance by circuit designers.